Simulation Methodology to Compare Emerging Technologies for Alternatives to Silicon Gigascale

JIN, YAWEI. Simulation Methodology to Compare Emerging Technologies for Alternatives to Silicon Gigascale Logic Device. (Under the direction of Dr. D. W. Barlage). Practical realization of low-power, high-speed transistor technologies for future generation nano-electronics can be achieved with novel structures, such as FinFET, tri-gate or with the integration of exotic channel materials, such as Gallium Nitride (GaN), into Fully-Depleted SOI (FDSOI) transistor architectures. Novel Structures are the most promising candidates for logic devices with sub20nm gate length. There’s two kinds of novel structures: planar structure and non-planar structure. Planar structure includes ultra-thin body single gate MOSFET and double gate MOSFET. Multi-gate structure architecture, such as FinFET, tri-gate, are major nonplanar structure. These novel structure can increase gate control and suppress short channel effects. To compare the feasibility of these different structures and to project the device performance, technology CAD (TCAD) simulation is a reasonable method. The III-V semiconductors, such as Gallium Nitride (GaN), have high maximum electron drift velocities and ballistic mean free paths, which would enable high-speed transistor operation at very low voltages with gate lengths below 10nm. Since it’s impractical for experiments currently, TCAD simulation can be used to project performance goals for aggressively scaled devices. This research focus on the methodology to compare different technologies for alternative to Silicon based traditional logic device using TCAD simulations. The methodology is called the “initialization-optimization-comparison” method. We first get different structure, process and electrical parameters from International Technology Roadmap for Semiconductor (ITRS) on specific technology node to initialize our TCAD simulation for different application, such as High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic. Then we developed an optimization procedure to optimize different device structure parameters, such as spacer width, body thickness, gate metal work function etc. and process parameters, such as source/drain doping abruptness, source/drain doping concentration, channel doping concentration etc. From simulation results, we compare different performance merits, power merits and other merits between these technologies and ITRS requirements. The technologies in this study include novel structures, such as ultra-thin body planar single-gate and double-gate MOSFET, non-planar FinFET and tri-gate FDSOI MOSFET, Indium Antimonide (InSb) based MOSFET and Gallium Nitride (GaN) based MOSFET. Other technologies can be studied using the same simulation procedure and methodology used in this research. Simulation Methodology to Compare Emerging Technologies for Alternatives to Silicon Gigascale Logic Device